1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming conductive contacts to the source/drain regions of FinFET devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
One problem encountered in manufacturing FinFET devices will now be described with reference to FIGS. 1A-1F. FIG. 1A is a perspective view of an illustrative FinFET semiconductor device 10 that is formed above a semiconducting substrate 12. The device 10 includes a plurality of fins 14, a gate electrode 13, sidewall spacers 17 and a gate cap layer 15. FIG. 1A depicts the locations where various cross-sectional views of the device 10 will be taken in the drawings discussed below. More specifically, view “X-X” is a cross-sectional view taken through the gate electrode 13 in a direction that is parallel to the long axis of the gate electrode 13, i.e., in the gate width direction, view “Y-Y” is a cross-sectional view taken through the fins 14 in a direction that is transverse to the long axis of the fins 14 and view “Z-Z” is a cross-sectional view taken along the long axis of one of the fins 14. It should be understood that FIG. 1A is only provided to show the location of the various cross-sectional views depicted in the drawings below, and many aspects discussed below are not depicted in FIG. 1A so as to not overly complicate the device 10 depicted in FIG. 1A. Moreover, the reference numbers employed below for various structures may not match the reference numbers depicted in FIG. 1A.
FIGS. 1B-1C depict the illustrative situation where an N-type FinFET device will be formed adjacent to a P-type FinFET device, such as in an SRAM structure, and where the two devices will ultimately share a common gate structure. The N-type FinFET device is separated from the P-type FinFET device by an illustrative shallow trench isolation region 14 that is formed in the substrate 12. Illustrative isolation regions 16 are also depicted. In the depicted example, the common gate structure for both devices will be formed using a so-called “replacement gate” or “gate last” technique. As it relates to forming conductive contacts to the source/drain regions of a FinFET device, there are basically two different techniques that device manufacturers employ. One technique, described below with reference to FIG. 1B, generally involves performing a so-called “fin merge” process and forming a substantially planar metal silicide region on top of the “merged fins.” Another technique generally involves forming a metal silicide region that “wraps around” the fins, as described below with reference to FIG. 1C. In both cases, a conductive contact material is then formed so as to conductively contact the metal silicide regions. However, merged fins are typically not desirable in designs where the space between the fins of different voltage node is tight, e.g., SRAM designs and high density logic designs, since merged fins limits the density of such designs.
At the point of fabrication depicted in FIG. 1B, a plurality of fins 18N have been formed for the N-type FinFET device and a single fin 18P has been formed for the P-type FinFET device. The fins were formed by performing an etching process, such as a dry or wet etching process, through a patterned mask layer (not shown) to form a plurality of trenches 13 in the substrate 12 to thereby define the fins 18N, 18P. Also depicted in FIG. 1B is a sacrificial gate structure that is comprised of a sacrificial gate insulation layer 20, a sacrificial gate electrode 22 and a gate cap layer 24. A sidewall spacer 25 is also depicted in FIG. 1B. Such structures and layers may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 20 may be comprised of silicon dioxide, the sacrificial gate electrode layer 22 may be comprised of polysilicon or amorphous silicon and the gate cap layer 24 may be comprised of silicon nitride. The layers of material depicted in FIG. 1B may be formed by any of a variety of different known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, etc. The sacrificial gate structure may be formed by patterning the layers of material using traditional photolithography and etching processes. The gate cap layer 24 is typically relatively thick, e.g., about 40-80 nm, due to the etching processes it must withstand as the device is being fabricated, as discussed more fully below. The sidewall spacer 25 may have a base thickness of about 10 nm and it may be comprised of materials such as silicon nitride, silicon oxynitride, silicon nitride carbon, etc.
FIG. 1B depicts the device 10 after semiconducting materials 19N, 19P have been formed on the fins 18N, 18P, respectively, by performing known epitaxial deposition processes. The diamond-shaped nature of the semiconductor materials 19N, 19P is due to the crystalline structure of the substrate material. Dashed lines depict the outline of the original fins 18N, 18P. Thereafter, an epitaxial deposition process is performed so as to form a relatively large region of semiconducting material 26 that effectively merges the individual fins together and forms the source/drain regions for the device 10. Thereafter, a metal silicide region 28, e.g. nickel silicide, etc., is formed on the substantially planar upper surface of the semiconductor material 26 using known techniques, i.e., refractory metal deposition, heating to cause reaction between the refractory metal layer and contacted silicon regions, followed by removal of unreacted refractory metal. Metal silicide regions are typically formed in the source/drain regions of a transistor to reduce the resistance when a conductive contact is formed to establish electrical connection to the source/drain regions. The metal silicide regions 28 depicted herein may be made using a variety of different refractory metals, e.g., nickel, platinum, cobalt, etc., or combinations thereof, and they may be formed using techniques that are well known to those skilled in the art. A conductive contact (not shown in FIG. 1B) is formed so as to conductively contact the metal silicide region 28.
FIG. 1C generally depicts the structure resulting from performing the above-mentioned wrap-around techniques to form a metal silicide region and a conductive contact to the source/drain regions of the device 10. In this example, after the diamond-shaped semiconductor material 19N, 19P are formed, the metal silicide material 28 is formed on the exposed portions of the diamond-shaped fins 19N, 19P. Using this wrap-around technique, the previously described fin merge process is not performed. Thus, the metal silicide material 28, and the conductive contact material (not shown in FIG. 1C) wraps around the exposed portions of the diamond-shaped fins 19N, 190P. FIG. 1C, view “Y-Y” includes a dashed line depicting the upper surface 20S of the sacrificial gate insulation layer 20.
One problem that results from the above process sequence is, at least with a nickel silicide material, the nickel tends to diffuse under the spacers toward the gate. Such diffusion is sometimes referred to in the industry as “silicide pipes.” When present, such silicide pipes can be detrimental to device performance as it creates an unwanted conductive path for current to flow. The problem is not as bad when dealing with FinFET devices in which the fins have been merged, as shown in FIG. 1B, because the metal silicide material 28 is spaced relatively far away from the channel region, as reflected by the double arrowed line 30 in FIG. 1B (view Z-Z). However, when the metal silicide regions 28 are formed on the fins of a FinFET device using the wrap-around approach, as shown in FIG. 1C, the metal silicide regions 28 are much closer to the channel region of the device, in the region indicated by the dashed line 32. Thus, the chance of the formation of such silicide pipes is greater when the wrap-around silicide formation process is used as compared to the merged fin/silicide formation process described above. The industry has attempted to combat this problem by using nickel/platinum-based metal silicides, wherein the platinum is present in concentrations of about 1-10%. However, even when used with platinum, the nickel material still has a tendency to diffuse under the spacer, particularly when there is insufficient healing of implant damage or a strain is present due to the silicon nitride spacer contacting silicon.
The present disclosure is directed to methods of forming conductive contacts to the source/drain regions of FinFET devices that may solve or reduce one or more of the problems identified above.